Electrically programmable logic array

ABSTRACT

An electrically programmable logic array (10) for binary signals having signal inputs A 0  -A x ) and signal outputs Q 0  -Q i ) comprises two row lines (a 0 ,a 0&#39;  -a x , a x&#39; ) for each signal input. The signal applied to the signal input is generatable at the one row line in non-negated form and at the other row line in negated form. For each signal output a column line (q 0  -q i ) is provided. 
     In the non-programmable state between each row line and each column line there is an electrically conductive connection interruptable for the purpose of programming. Inserted into the connection between the signal inputs and each associated row line is a controllable switching member (S 0 ,S 0&#39; ,-S x , S x&#39; ) which is controllable by a control signal applied thereto in such a manner that its output signal changes with the signal applied to the associated signal input or irrespective of said signal always retains a predetermined signal value.

The invention relates to an electrically programmable logic array forbinary signals having signal inputs and signal outputs, two row linesfor each signal input, the signal applied to the signal input beinggeneratable at the one row line in non-negated form and at the other rowline in negated form, a column line for each signal output and aconnection between each row line and each column line which iselectrically conductive in the non-programmed state and interruptablefor the purpose of the programming.

An electrically programmable logic array of the type mentioned at thebeginning is contained for example in the integrated circuit of the typeSN54TL16R4 made by Texas Instruments. A description of this integratedcircuit will be found in the manual issued by this company "ALS/AS LogicCircuit Data Book 1983" on pages 3/10. In English-language literature alogic matrix of this type is generally referred to as "programmablelogic array" (abbreviated to PLA). In one use, such a logic array isused in addressing a memory for obtaining a a 1-from-N decoding from theresult of which in each case a selection signal is applied to anindividual memory address line when a specific memory address associatedwith said address line appears at an address bus connected to the logicarray.

To enable the known logic array to be used as universally as possibletwo row lines are associated with each signal input and by suitablecircuitry measurement is ensured that at the one row line the binaryvalue corresponding to the binary value at the signal input appearswhilst at the other row line the negated binary value appears. Via theelectrically conductive connections, interruptable for programmingpurposes, between the row conductor and the column conductors it is thuspossible to apply to each column conductor an input signal innon-negated form or also in negated form. In the programmed state, i.e.when some of the originally electrically conductive connections betweenthe row conductors and the column conductors have been interrupted inaccordance with the desired decoding function, the column conductorsbehave like AND circuits, which means that at the output connected tothe column conductor a signal with the binary value "H" appears onlywhen this binary value "H" is present at all row conductors connected tosaid column conductor. As soon as the binary value "L" appears at a rowconductor connected to said column conductor the signal at the outputconnected to said column conductor also assumes the value "L".

Both from the point of view of the manufacturer and from the point ofview of the user it is desirable to check a programmable logic arraybefore executing a program to determine whether the electricallyconductive connections between the row conductors and the columnconductors are all perfect, i.e. are not interrupted. Only when anelectrically conductive connection is present in the non-programmedstate between each signal input and each signal output is it ensuredthat the logic array can be programmed in any desired manner to obtaindesired decoding functions. With the known logic array it is notpossible to check the electrical connections between the row conductorsand the column conductors individually because as soon as binary signalsare applied to the signal inputs, to each column conductor by the tworow conductors associated in each case with a signal input both thebinary value "H" and the binary value "L" is applied. Since the circuitswhich connect the signal inputs to the row conductors are so formed thattheir output signal assumes the binary value "L" irrespective of theirinput signal when such a binary value reaches their output from anothercircuit, at all signal outputs the binary values "L" always occur andthese binary values are also applied to the signal inputs. It istherefore not possible to selectively check an electrical connectionbetween a selected row conductor and a selected column conductor.

The problem underlying the invention is to further develop a logic arrayof the type outlined in such a manner that the electrical connectionsexisting in the non-programmed state between the row conductors and thecolumn conductors can be individually checked prior to programming.

According to the invention this problem is solved in that into theconnection between the signal input and each of the row conductorsassociated with said inputs a controllable switching member is insertedwhich is controllable by a control signal applied thereto in such amanner that its output signal changes with the signal applied to theassociated signal input or irrrespective of said signal always retains apredetermined signal value.

In the logic array according to the invention with the aid of thecontrollable switching members the possibility is provided of generatingat all row conductors tne same selected signal value by applyingpreselected signal values to the signal inputs. One of two switchingmembers associated with a respective signal input is in the state inwhich its output signal varies in dependence upon the signal applied tothe associated signal input. A change of the signal value applied to asignal input can therefore be detected at the signal outputs which areconnected via column conductors and the electrically conductiveconnections to the line conductor at which the changing signal valueoccurs. It is thereby possible to check consecutively all the electricalconnections between the row conductors and column conductors for theirfunctionability. The signal paths between the signal inputs and theassociated signal outputs can also be checked both as regards theirfunctionability and as regards their switching speed. The invention willnow be explained by way of example with the aid of the drawing, thesingle FIGURE of which shows a schematic circuit diagram of the partessential to the invention of an electrically programmable logic array.

The invention is illustrated by a single FIGURE

The logic array 10 illustrated in the drawing has signal inputs A₀ toA_(x) and signal outputs Q₀ to Q_(i). Associated with each signal inputare two row conductors a₀ and a₀ ', a₁ and a₁ ' . . . a_(x) and a_(x) '.Its signal output is connected to a column conductor q₀, q₁ . . . q_(i).

In the non-programmed state of the logic array 10 between each rowconductor a_(o), a_(o) ' . . . a_(x), a_(x) ' and each column conductorq₀ to q₁ an electrically conductive connection formed in each case by afuse bridge F and a diode D is present. Using circuits not illustratedin the drawing and connected to the column conductors, and by applyingspecific programming signals, the fuse bridges can be destroyed inselected manner for programming the logic array 10 in order to interruptthe connection between a selected row conductor and a selected columnconductor. The manner in which the programming operation is carried outis known and consequently no details thereon will be given here. Thediodes D serve for decoupling to "L" and "H" signals at the columnconductors q_(o), q₁ . . . q_(i).

Each signal input A₀ to A_(x) is connected via a negator N₀ to N_(x) toan input of a switching member S₀, S₁ . . . S_(x) formed by a NANDcircuit. Furthermore, each signal input A₀ to A_(x) is connecteddirectly to an input of a further switching member S₀ ', S₁ ' . . .S_(x) ' likewise formed by a NAND circuit. The second inputs of theswitching members S₀, S₁ . . . S_(x) are connected directly to a controlinput C₁ and the second inputs of the switching members S₀ ', S₁ ' . . .S_(x) ' are connected jointly to a control input C₂.

The following procedure is adopted in order to check in the logic array10 described whether the fuse bridges F each connecting a row conductorand a column conductor do indeed in fact establish the desiredconnection:

To the control input C₁ a signal with the value "H" is applied and tothe control input C₂ a signal with the value "L". At the same timesignals with the value "H" are applied to all the signal inputs A₀ toA_(x).

For the further explanation the signals at the components N₀, S₀ and S₀' associated with the signal input A₀ and at the row conducts a₀ and a₀' will first be considered in detail. The signal with the value "H" atthe signal input A₀ results, due to the negating by the negator N₀, inthe signal value "L" appearing at the first input, shown at the top inthe drawing, of the switching member S₀. At the second input of theswitching member S₀ there is the already mentioned control signal fromthe control input C₁ with the value "H". Since as already mentioned theswitching member S₀ is a NAND circuit, and its output connected to therow conductor a₀ a signal with the value "H" appears. At both inputs ofthe switching member S₀ ' there are signals with the value "L" so thatthis switching member as well also furnishes at its output a signal withthe value "H" and applies it to the row conductor a₀ '. By applicationof this signal with the value "L" to the second input of the switchingmember S₀ ' the latter furnishes at its output the signal value "H"irrespective of which signal is applied to its first input by the signalinput A₀. This means that at the row conductor a₀ ' there is always thesignal value "H" irrespective of the signal at the signal input A₀.

On the other hand, at the second input of the switching member S₀ thereis the signal value "H" and as a result at its output and thus also atthe row conductor a₀ the signal value "H" or the signal value "L" can begenerated depending on whether the signal value "H" or "L" is applied tothe signal input A₀. The conditions outlined above are also present atthe components associated with the other signal inputs A₁ to A_(x) andat the corresponding row conductors.

As apparent from the circuit diagram the outputs of all the switchingmembers S₀, S₀ ' to S_(x), S_(x) ' are connected via the fuse bridgesF₀₀, F₀₀ to F_(x0), F_(x0) in parallel to the signal output Q₀. As longas the signal value "H" is also present at all the row conductors thesignal value "H" appears at this output Q₀. However, as soon as thesignal value "L" appears at one row conductor the signal at the signaloutput Q₀ also assumes the value "L". From the point of view of thelogic function the outputs of the switching members S₀, S₀ ' to S_(x),S_(x) ' are each connected via an AND circuit to the signal outputs Q₀to Q_(i).

For checking the function state of the fuse bridge F₀₀ the signal at thesignal input A₀ is switched from the signal value "H" to the signalvalue "L". If the signal at the signal output Q₀ follows this changefrom "H" to "L" the fuse bridge F₀₀ is in order, i.e. it establishes aconnection between the row conductor a₀ and the column conductor q₀. Itis now possible to determine consecutively whether the same change from"H" to "L" also occurs at the signal outputs Q₁ to Q_(i), it therebybeing possible to check in succession the fuse bridges F₀₁ to F_(0i).For checking the fuse bridges present between the row conductor a₁ andthe column conductors q₀ to q_(i) a signal with the value "L" is appliedonly to the signal input A₁ and it is determined whether the resultingchange from "H" to "L" also occurs at the outputs Q₀ to Q_(i). In thismanner, in succession it is possible to check for their satisfactorystate all the fuse bridges present between the row conductors a₀ toa_(x) and the column conductors q₀ to q_(i).

For checking the fuse bridges between the row conductors a₀ ' to a_(x) 'and the column conductors q₀ to q_(i) the signal value "L" is applied tothe control input C₁ and the signal value "H" is applied to the signalinput C₂. As in the test previously described at all signal inputs A₀ toA_(x) signals with the value "H" are again applied. As a result, at allrow conductors signals with the value "H" are applied. However, in thiscase the switching members S₀ to S_(x) by the control signal with thevalue "L" at their second input are put into a state in which theiroutput signal always retains the value "H" irrespective of the value ofthe signal applied to their first input. In contrast the switchingmembers S₀ ' and S_(x) ' react to a change of the signal value at theirfirst input from "H" to "L" with a corresponding change of their outputsignal. In the manner described above it is now possible to check insuccession the fuse bridges present between the row conductors a₀ ' anda_(x) ' and the column conductors q₀ to q_(i) by switching over thesignal values at the signal inputs A₀ to A_(x) from "H" to "L" anddetecting a corresponding signal value change at the signal outputs Q₀to Q_(i).

By inserting the switching members S₀, S₀ ' to S_(x), S_(x) ' into theconnections between the signal inputs A₀ to A_(x) and the row conductorsa₀, a_(O) ' to a_(x), a_(x) ' it is possible in the manner outlined tocheck the conductive state of all the fuse bridges present in theunprogrammed state between the row conductors and the column conductorsq₀ to q_(i). This function test provides the user with the certaintythat before programming he has at his disposal a perfect logic array 10so that by the programming carried out by selective interruption of thefuse bridges the desired function of the logic array can indeed beachieved. When using the logic array in the programmed state, to thecontrol inputs C₁, C₂ signals with the value "H" are applied by whichthe switching members S₀, S₀ ' to S_(x), S_(x) ' are put into the statein which they vary their output signal in dependence upon the signalapplied to their first input.

What is claimed is:
 1. Electrically programmable binary logic arrayhaving signal inputs and signal outputs, comprising in combination tworow lines for each signal input, means for generating the signal inputat the one row line in true form and at the other row line in complementform, a column line for each signal output, a connection between eachrow line and each column line which is electrically conductive in thenon-programmed state and interruptable for the purpose of theprogramming, a controllable switching member between the signal inputsand each of the row conductors, and means for applying a control signalthereto in such a manner that its output signal changes with the signalapplied to the associated signal input or irrespective of said signalalways retains a predetermined signal value.
 2. Logic array according toclaim 1, characterized in that the switching members are NAND circuitswhich have two inputs, of which in each case one is connected to theassociated signal input and the other is connected to one of two controlinputs.